This invention relates to a solid-state imaging device, and more particularly to a circuit for suppressing leakage current at the signal storage nodes of a CMOS solid-state image sensor (CMOS image sensor) with a read circuit capable of reading an image signal pixel by pixel, a circuit of suppressing the current drawn by an image signal amplifying source follower, and a horizontal readout gate providing a horizontal signal line with less parasitic capacitance, which are used in, for example, a video camera or an electronic still camera.
FIG. 20 shows an equivalent circuit of a conventional CMOS solid-state image sensor (amplification CMOS image sensor) (conventional equivalent 1) with a read circuit capable of reading an image signal pixel by pixel.
In the sensor of FIG. 20, a cell area (imaging area) 1 is composed of plural unit cells 13 arranged in a two-dimensional matrix. One unit cell corresponds to one pixel.
Each unit cell 13 is composed of, for example, four transistors and one photodiode. Specifically, each unit cell 13 includes a photodiode 8 to whose anode the ground potential is applied, a read transistor (shutter gate transistor) 14 one end of which is connected to the cathode of the photodiode 8, an amplifying transistor 15 whose gate is connected to the other end of the read transistor 14, a vertical select transistor 16 one end of which is connected to one end of the amplifying transistor 15, and a reset transistor 17 one end of which is connected to the gate of the amplifying transistor 15. In the cell area 1, the following lines are formed: read lines connected in common to the gates of the individual read transistors of the unit cells in the same rows, vertical select lines 6 connected in common to the gates of the individual read transistors 14 of the unit cells in the same rows, reset lines 7 connected in common to the gates of the individual reset transistors of the unit cells in the same rows, vertical signal lines 18-i (i=1 to n) connected in common to the other end of the individual amplifying transistors 15 of the unit cells in the same columns, and power lines 9 connected in common to the other end of the individual reset transistors and to the other end of the individual vertical select transistors 16 of the unit cells in the same columns.
Outside the cell area 1, the following component parts are provided: load transistors 12 connected between one end of the respective vertical signal lines 18-i and the ground nodes, horizontal select transistors 23-i one end of which is connected to the other end of the respective vertical signal lines 18-i via the corresponding noise chancellor circuits 25-i, a horizontal signal line 26 connected in common to the other end of the horizontal select transistors 23-i, an output amplifier circuit 27 connected to the horizontal signal line 26, a horizontal reset transistor 28 connected to the horizontal signal line 26, a vertical shift register 2 for supplying a select signal in a scanning manner to the vertical select lines 6 of each row in the cell area 1 and driving the vertical select transistors 16 in each row in a scanning manner, a horizontal register 3 for driving the horizontal select transistors 23-i in a scanning manner, and a timing generator circuit 10 for generating various timing signals.
Each of the noise chancellor circuits 25-i is composed of, for example, two transistors and two capacitors. Specifically, each noise chancellor circuit is composed of a sample hold transistor 19 one end of which is connected to the other end of the vertical signal line 18-i, a coupling capacitor 20 one end of which is connected to the other end of the sample hold transistor 19, a charge accumulation capacitor 21 connected between the other end of the coupling capacitor 20 and the ground node, and a potential clamping transistor 22 connected to the junction node of the capacitors 20, 21. One end of the corresponding one of the horizontal select transistors 23-i is connected to the junction node of the capacitors 20, 21.
Each of the horizontal select transistors 23-i is made up of an NMOS transistor having an active region (SDG region) formed in a p-well selectively formed at the surface of a semiconductor substrate. The p-well is connected to the ground potential.
FIG. 21 is a timing waveform diagram to help explain the operation of the solid-state image sensor of FIG. 20. Referring to FIG. 21, the operation of the solid-state image sensor of FIG. 20 will be explained.
The incident light on each photodiode 8 is converted photoelectrically and the resulting signal charges are accumulated in the photodiodes 8.
Before the operation of reading the signal charge, a high reset signal is applied to the reset line 7 for a specific period of time to reset the gate potential of the amplifying transistor 15. The reset transistor 17 is on for the specific period, resetting the gate potential of the amplifying transistor 15 to a desired potential.
At the same time, a high select signal is supplied to the vertical select line (address line) 6 selected in a scanning manner by the vertical shift transistor 2. The select signal from the vertical select line 6 turns on the vertical select transistor 16. The power supply line 9 supplies a voltage to the amplifying transistor 15 via the vertical select transistor 16. This causes the source-follower-connected amplifying transistor 15 to output a potential proportional to its gate potential to the corresponding vertical signal line 18-i.
There is a variation in the gate potential of the reset amplifying transistor 15. As a result, a variation appears in the reset potential of the vertical signal line 18-i connected to the drain of the amplifying transistor 15.
To reset the variation in the reset potential of each vertical signal line 18-i, the sample hold transistor 19 is turned on after the reset transistor 17 has been turned on. As a result, the reset potential of the vertical signal line 18-i is transmitted to the capacitor 21 via the capacitor 20. Thereafter, the potential clamping transistor 22 is kept on for a specific period, fixing the voltage of the junction node of the capacitors 20, 21 at a constant level.
Next, the read line 4 corresponding to the desired row is selected (or supplied with a high read signal), turning on the read transistor 14. This causes the accumulated charge in the photodiode 8 to be transferred to the gate of the amplifying transistor 15 via the read transistor 14, which changes the gate potential. The amplifying transistor 15 outputs a voltage signal proportional to the amount of change of the gate potential to the corresponding vertical signal line 18-i.
As a result, the change in the voltage signal on the vertical signal line 18-i caused by the read operation after resetting has been transferred to the capacitor 21 via the capacitor 20. This removes the noise introduced in the stages before the noise chancellor circuit 25-i, such as variations in the reset potential of each vertical signal line 18-i occurring in the cell area 1.
After the noise removing operations have been carried out, the sample hold transistor 19 is turned off and the vertical select transistor 16 is also turned off. As a result, the unit cell 13 is brought into the unselected state and the cell area 1 is electrically disconnected from each noise chancellor circuit 25-i.
Then, the horizontal reset transistor 28 is turned on, which resets the horizontal signal line 26. Thereafter, the horizontal select transistors 23-i are turned on sequentially, causing the voltages at the junction nodes (signal storage nodes SN) of the capacitors 20, 21 to be read sequentially. The read-out voltages are amplified by the output amplifier circuit 27, which then outputs the amplified voltages.
The above-described noise removing operations are carried out each time one horizontal line is read from.
In the prior art, after the series of noise removing operations has been completed, the vertical select line 6 is returned to the low level, turning off the vertical select transistor 16. As a result, the voltage of the vertical signal line 18-i drops to the ground potential via the load transistor 12. At this time, since one end of the vertical signal line 18-i of the sample hold transistor 19 is biased at the same voltage as that of the substrate (e.g., the p-well) in the noise chancellor circuit 25-i, as much leakage current as cannot be neglected develops. The leakage current changes the voltage at the signal storage node SN.
In this case, the leakage currents in the individual sample hold transistors 19 differ from one another. This permits the amount of change of the voltage at the signal storage node SN to differ with the leakage current.
Thereafter, the horizontal select transistors 23-i are tuned on sequentially and the signal is read from each horizontal select transistor 23-i. Since the direct-current potentials of the read-out signals differ from each other, image noise, such as vertical lines, takes place due to the variations in the direct-current potential when the output signal of the image sensor is displayed on the screen of the image display unit.
Additionally, in the prior art, the potentials of the signal storage nodes SN are clamped in the noise chancellor circuits 25-i, the potentials are clamped at the ground potential by the clamp transistors 22. One end of the clamp transistors 22 and that of the horizontal select transistors 23-i connected to the signal storage nodes SNs are biased at the same voltage as that of the substrate (the p-well in the example). This permits as much leakage current as cannot be neglected to take place at those transistors.
As a result, when the horizontal select transistors 23-i are turned on sequentially, the direct-current potentials of the signals of the horizontal select transistors 23-i later selected vary from the direct-current potential of the signal read from the horizontal select transistors 23-i earlier selected (for example, the former get lower gradually). As a result, image noise, such as vertical lines, occurs.
FIG. 22 shows an equivalent circuit of another conventional amplification CMOS image sensor (conventional equivalent 2).
In FIG. 22, in a cell area (imaging area) 1, unit cells 13 are arranged in a two-dimensional matrix. Like the unit cell 13 of FIG. 20, each unit cell 13 in conventional equivalent 2 is composed of a vertical select transistor (row select transistor) Ta, an amplifying transistor Tb, a reset transistor Tc, a read transistor Td, and a photodiode PD. One pixel is made up of one unit cell 13.
As in FIG. 22, read lines 4, vertical select lines 6, reset lines 7, vertical signal/lines VLIN, and power supply lines 9 are formed in the cell area 1.
As in FIG. 22, a load transistor TL is connected between one end of the vertical signal lines VLIN and the ground node outside the lower part of the cell area 1.
Like the noise chancellor circuits 25-i of FIG. 20, noise chancellor circuits 25 are arranged in the horizontal direction outside the upper part of the cell area 1. Each noise chancellor circuit is composed of a sample hold transistor TSH, a potential clamping transistor TCLP, a coupling transistor Cc, and a charge accumulation capacitor Ct. A horizontal select transistor TH one end of which is connected to the junction node of the capacitor Cc and capacitor Ct is provided for each noise chancellor circuit.
A horizontal signal line HLIN is connected in common to the other end of each of the horizontal select transistors TH. A horizontal reset transistor (now shown) and an output amplifier circuit (not shown) are connected to the horizontal signal line HLIN.
Furthermore; outside the cell area 1, the following are provided: a vertical shift register 2 for selecting the vertical select transistors Ta in each row in a scanning manner, a horizontal shift register 3 for driving the horizontal select transistors TH in a scanning manner, a timing generator circuit for generating various timing signals to be supplied to, for example, the noise chancellor circuit 25, a bias generator circuit 11 for supplying a specific bias potential to one end of the potential clamping transistor TCLP of the noise chancellor circuit 25, and a pulse selector 2a for driving the individual rows in the cell area 1 in a scanning manner under the control of the output pulse from the vertical shift register 2.
In FIG. 22, the amplifying transistor Tb of each unit cell 13 and the load transistor TL connected to the amplifying transistor Tb via the vertical signal line VLIN constitute a source follower amplifier circuit.
The operation of the solid-state image sensor of FIG. 22 is basically the same as that of the solid-state image sensor of FIG. 20 except for operation timing.
FIG. 23 is a timing waveform diagram to help explain the operation of the solid-state image sensor of FIG. 22.
In each unit cell 13, incident light on the photodiode PD is converted photoelectrically. The resulting signal charges are accumulated within the photodiode PD.
To read the signal charges in the photodiodes PD from the unit cells 13 in a row (hereinafter, referred to as a selected row) in the horizontal retrace line interval, the signal (xcfx86 ADRES pulse) to the vertical select line 6 for the selected row is turned on, turning on the row select transistors Ta in the selected row, to select each of the vertical signal lines VLIN.
This causes the source follower circuit composed of the amplifying transistor Tb supplied with the power-supply potential VDD via the row select transistor Ta and the load transistor TL to operate in the individual unit cells 13 in the selected row.
Next, in each unit cell in the selected row, the signal (xcfx86 RESET pulse) to the reset line 7 is turned on to reset the gate voltage of the amplifying transistor Tb to a reference voltage, thereby outputting the reference voltage to the vertical signal line VLIN.
In this case, the driving signal (xcfx86 SH pulse) of the sample hold transistor TSH in the noise chancellor circuit 25 is turned on in advance (for example, at the same time the (xcfx86 ADRES pulse is turned on). After the reference voltage has been outputted to the vertical signal line VLIN, the driving signal (xcfx86 CLP pulse) of the potential clamping transistor TCLP is kept on for a specific period of time, which sets the reference voltage in the noise chancellor circuit 25.
Next, after the PRESET pulse has been turned off, the signal (xcfx86 READ pulse) on the read line 4 is turned on. This turns on the read transistor Td, supplying a voltage proportional to the accumulated charges in the photodiode PD to the gate of the amplifying transistor Tb. As a result, the signal voltage proportional to the accumulated charges is outputted to the vertical signal line VLIN and noise chancellor circuit 25.
Thereafter, the xcfx86 SH pulse in the noise chancellor circuit 25 is turned off, which allows the signal component (noise-removed signal voltage) corresponding to the difference between the reference voltage and the read-out signal voltage to be accumulated in the charge accumulating capacitor Ct even in the effective horizontal scanning period.
Then, after the cell area 1 has been electrically separated from each noise chancellor circuit 25, the signal voltage accumulated in the capacitor Ct turns off xcfx86 ADRES pulse in the effective scanning period, turning off the vertical select transistor Ta, which places the unit cells 13 in the selected row in the unselected state. Thereafter, sequentially turning on the driving signals (xcfx86 H pulse) for the horizontal select transistors TH causes the horizontal select transistors TH to turn on in sequence, allowing the signal voltage accumulated on the horizontal signal line HLIN to be outputted.
In the operation, the voltage VVLIN of the vertical signal line VLIN becomes the operating voltage Vm (about 1.5V) of the source follower circuit in the horizontal retrace line interval, whereas it becomes 0V in the effective horizontal scanning period. This permits leakage current from the sample hold transistors TSH to occur in the effective horizontal scanning period and enter the capacitors of the noise chancellor circuit 25. The leakage current differs from one vertical line to another, which causes image noise, such as vertical lines.
As described above, the conventional CMOS image sensors have the problem of permitting image noise, such as vertical lines, to appear on the display screen of the image sensor output signal as a result of changes in the voltage at the signal storage node caused by the current leakage after a series of noise removing operations has been completed by the noise chancellor circuit in a read operation for each horizontal line.
FIG. 25 shows patters of part of the horizontal readout gate section of the conventional CMOS image sensor of FIG. 20.
In FIG. 25, reference symbol 23a-i (i=1 to 4) indicates the active region (SDG region) of the horizontal select transistor 23-i formed in a p-well selectively formed at the surface of a semiconductor substrate. Element isolating regions 24 are formed between SDG regions.
Reference symbol 23b-i indicates the gate electrode (polysilicon wire) of the horizontal select transistor 23-i. The gate electrode is formed on the channel of the SDG region 23a-i via a gate insulation film (not shown) formed at the surface of the p-well.
A metal wire (normally an aluminum wire) corresponding to the vertical signal line 18-i is connected to the n-type diffused region (source) at one end of the SDG region 23a-i. To the n-type diffused region (drain) at the other end, a metal wire (normally an aluminum wire) corresponding to the horizontal signal line 26 is connected.
Since the coupling capacitance with the p-well is present in the n-type diffused regions acting as the drain and source of the horizontal select transistor 23-i, the parasitic capacitance 29 on the horizontal signal line 26 increases in proportion to the number of the horizontal select transistors 23l-i.
The increase in the parasitic capacitance on the horizontal signal line 26 makes the operating speed of the circuit slower. Switching noise developing as a result of the switching operation of the horizontal select transistor 23-i is not removed by the noise chancellor circuit 25-i and enters the parasitic capacitance 29. The amount of incoming noise becomes larger as the parasitic capacitance increases. The larger amount of incoming noise contributes the occurrence of image noise, such as vertical lines when the output signal of the solid-state image sensor is displayed on the screen of the image display unit.
As described above, the conventional solid-state image sensor has the problem of making the circuit operation speed slower because the parasitic capacitance of the horizontal signal line increases in proportion to the number of horizontal select transistors and of permitting image noise, such as vertical lines, to appear on the display screen of the output signal from the image sensor as a result of noise entering the parasitic capacitance.
Accordingly, objects of the present invention is to solve the problems described above.
According to the present invention, there is provided a solid-state imaging device capable of suppressing not only current leakage occurred after a series of noise removing operations by noise chancellor circuits has been completed in a read operation for each horizontal line, but also image noise, such as vertical lines, appearing on the display screen of the output signal of an image sensor.
Furthermore, according to the present invention, there is provided a solid-state imaging device capable of reducing the parasitic capacitance at the horizontal signal lines dependent on the number of horizontal select transistors to speed up the circuit operation and decreasing the amount of noise entering the parasitic capacitance to suppress image noise, such as vertical lines, appearing on the display screen of the output signal of the image sensor because of the incoming noise.
Specifically, according to a first aspect of the present invention, there is provided a solid-state imaging device comprising: an imaging area including units cells arranged in a two-dimensional matrix on a semiconductor substrate and vertical signal lines each connected in common to the unit cells in the same row, each unit cell comprising: a photoelectric conversion element for generating charges in proportion to incident light; a read circuit for reading a voltage corresponding to the generated charges, an amplifier circuit for amplifying the read-out voltage; a reset circuit for resetting the generated charges; and a row select circuit for allowing the output signal of the amplifier circuit to be output onto the vertical signal line; load transistors each being connected to corresponding one of the vertical signal lines at one end; a load transistor on/off circuit for controlling the load transistors in a manner such that the load transistors are turned off when the row select circuit is in the off state; and signal storage circuits each being connected to corresponding one of the vertical signal lines at the other end, for storing a signal output onto corresponding one of the vertical signal lines, wherein: a bias voltage is applied to the vertical signal lines after the load transistor on/off control circuit has turned off the load transistors.
According to a second aspect of the present invention, there is provided a solid-state imaging device comprising: an imaging area including:
unit cells arranged in a two-dimensional matrix on a semiconductor substrate, each unit cell having a photoelectric conversion element; vertical signal lines each being connected in common to unit cells in the same column; and vertical select lines each being connected in common to unit cells in the same row, for selecting the unit cells in the same row; a driving circuit for selectively driving the vertical select lines; load transistors each being connected to corresponding one of the vertical signal lines at one end; signal storage regions each being connected to corresponding one of the vertical signal lines at the other end, for storing a signal readout on the corresponding one of the vertical signal lines; a horizontal signal line onto which signals stored in the signal storage regions are sequentially transferred; transistors each being connected to a signal path arranged between corresponding one of the vertical signal lines and the horizontal signal line and a bias voltage control circuit for biasing one of the drain and source of each of the transistors in the reverse direction with respect to the substrate region at least in a period during which the signals are transferred sequentially from the signal storage regions to the horizontal signal line.
According to a third aspect of the present invention, there is provided A solid-state imaging device comprising: an imaging area provided by arranging unit cells each including a photoelectric conversion element in a two-dimensional matrix on a semiconductor substrate; a row select circuit for selecting unit cells in the same row in the imaging area; vertical signal lines onto which signals read out from the unit cells in the same row selected by the row select circuit are transferred; a horizontal readout gate section for sequentially selecting the signals transferred onto the vertical signal lines, the horizontal readout gate section comprising: horizontal select transistors each being connected to corresponding one of the vertical signal lines, in which two adjacent ones of the horizontal select transistors form a plurality of pairs, each pair having a drain region commonly shared by the two adjacent transistors and connected to the horizontal signal line, and two source regions being arranged to sandwich the shared drain region; and a pair of correction transistors having a drain regions and source regions arranged in the same manner as each of the pairs, wherein when one transistor of a selected one of the pairs is driven, the pair of correction transistors are driven in a complementary manner with respect to the pair of horizontal select transistors.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.